Aitor Morillo Rascon, MSc

Berufliche Erfahrung

05/2011 - 03/2025
Team Leader - Med-El
Project Leader of a Vestibular Processor and accessories for market approval in the USA. Team leader of a 5-member team. Hardware and Firmware design of a Vestibular Processor for a first in Human study. Experience with implementation and testing according to medical standards (Safety, Security, EMC, Usability, Software life-cycle, etc.)

Ausbildung

01/2008 - 12/2010
MSc - University of the Basque Country (EHU)
Advanced Electronic Systems
01/2001 - 12/2008
Engineering - University of the Basque Country (EHU)
Telecommunication

Lehr- und Vortragstätigkeit

01/2024 - 12/2025
Bachelor - Management Center Innsbruck
Guest teacher for Usability und User Experience
01/2008 - 12/2010
UNED (Spanish National Distance Learning University)
Teacher on subjects of Informatics engineering and Industrial engineering. o Algebra o Mathematics extension o Logic mathematics o Discrete mathematics

Fortbildung & Training

2023 - 2023
Oxford University
Signal Integrity and Power Distribution
2017 - 2017
IREB
Certified Proffessional for Requirements Engineering/
2014 - 2014
Gantus
Project management for product development of medical devices

Veröffentlichungen in Fachzeitschriften (peer reviewed)

outros PJ, Schoo DP, Rahman M, Valentin NS, Chow MR, Ayiotis AI, Morris BJ, Hofner A, Rascon AM, Marx A, Deas R, Fridman GY, Davidovics NS, Ward BK, Treviño C, Bowditch SP, Roberts DC, Lane KE, Gimmon Y, Schubert MC, Carey JP, Jaeger A, Della Santina CC. Continuous vestibular implant stimulation partially restores eye-stabilizing reflexes. JCI Insight. 2019 Nov 14;4(22):e128397. doi: 10.1172/jci.insight.128397 [Titel anhand dieser DOI in Citavi-Projekt übernehmen] . PMID: 31723056 [Titel anhand dieser Pubmed-ID in Citavi-Projekt übernehmen] ; PMCID: PMC6948863. [Titel anhand dieser PMC-ID in Citavi-Projekt übernehmen] Format:

Beitrag in Konferenzband (peer reviewed)

A. Morillo, A. Astarloa, J. Lázaro, U. Bidarte and J. Jimenez, "Known-blocking. Synchronization method for reliable processor using TMR & DPR in SRAM FPGAs," 2011 VII Southern Conference on Programmable Logic (SPL), Cordoba, Argentina, 2011, pp. 57-62, doi: 10.1109/SPL.2011.5782625 [Titel anhand dieser DOI in Citavi-Projekt übernehmen] . keywords: {Synchronization;Random access memory;Tunneling magnetoresistance;Field programmable gate arrays;Microprocessors;Circuit faults;Process control},
A. Morillo, A. Astarloa, J. Lázaro, U. Bidarte and J. Jimenez, "Reliable microprocessors for FPGAs: State of the art and trends," 2010 International Conference on Applied Electronics, Pilsen, Czech Republic, 2010, pp. 1-6. keywords: {Synchronization;Microprocessors;Program processors;Field programmable gate arrays;Tunneling magnetoresistance;Redundancy;Fault tolerant systems},